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ALTERA FPGA SOC JTAG

Description

  1. Debugs all ALTERA FPGA SOC microcontrollers with JTAG interface supported by Qartus II
  1. High speed USB 2.0 interface
  2. Uses standard 2×10 PIN JTAG connector,can be extended to 14PIN,10PIN ,6PIN through adapter board.
  3. Working voltage range 1.8 – 5.0 V DC
  4. Dimensions 10.2x5.4 mm (2×1.6″) , Adapter plate 6pin, 2x7pin 2.54mm,15 cm (8″) 2×10 JTAG cable , 1×6 JTAG cable , 2×7 JTAG cable ribbon cable are included

Interface Signals

The JTAG interface, collectively known as a Test Access Port, or TAP, uses the following signals to support the operation of boundary scan.

  • TCK (Test Clock) – this signal synchronizes the internal state machine operations.
  • TMS (Test Mode Select) – this signal is sampled at the rising edge of TCK to determine the next state.
  • TDI (Test Data In) – this signal represents the data shifted into the device’s test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.
  • TDO (Test Data Out) – this signal represents the data shifted out of the device’s test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.
  • TRST (Test Reset) – this is an optional pin which, when available, can reset the TAP controller’s state machine.

Registers

There are two types of registers associated with boundary scan. Each compliant device has one instruction register and two or more data registers.

Instruction Register – the instruction register holds the current instruction. Its content is used by the TAP controller to decide what to do with signals that are received. Most commonly, the content of the instruction register will define to which of the data registers signals should be passed.

Data Registers – there are three primary data registers, the Boundary Scan Register (BSR), the BYPASS register and the IDCODES register. Other data registers may be present, but they are not required as part of the JTAG standard.

  • BSR – this is the main testing data register. It is used to move data to and from the I/O pins of a device.
  • BYPASS – this is a single-bit register that passes information from TDI to TDO. It allows other devices in a circuit to be tested with minimal overhead.
  • IDCODES – this register contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of the Boundary Scan configuration for the device.

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