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Xilinx Inc. XC7Z030-2FFG676I

The Zynq®-7000 family is based on the Xilinx All Programmable SoC architecture.

Xilinx Inc. XC7Z030-2FFG676I

These products integrate a feature-rich dual-core ARM® Cortex-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.

Key Features

  • Dual-core ARM® Cortex™-A9 Based Application Processor Unit (APU)
  • 2.5 DMIPS/MHz per CPU
  • CPU frequency: Up to 1 GHz
  • Coherent multiprocessor support
  • ARMv7-A architecture
  • TrustZone® security
  • Thumb®-2 instruction set
  • Jazelle® RCT execution Environment Architecture
  • NEON™ media-processing engine
  • Single and double precision Vector Floating Point Unit (VFPU)
  • CoreSight™ and Program Trace Macrocell (PTM)
  • Timer and Interrupts
  • 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)
  • 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
  • Byte-parity support
  • On-chip boot ROM
  • 256 KB on-chip RAM (OCM)
  • Byte-parity support
  • Multiprotocol dynamic memory controller
  • 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories
  • ECC support in 16-bit mode
  • 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories
  • Static memory interfaces
  • Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
  • Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints
  • Two SD/SDIO 2.0/MMC3.31 compliant controllers
  • Two full-duplex SPI ports with three peripheral chip selects
  • Two high-speed UARTs (up to 1 Mb/s)
  • Two master and slave I2C interfaces
  • GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the Programmable Logic
  • Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments
  • True Dual-Port
  • Up to 72 bits wide
  • Configurable as dual 18 Kb

Technical Attributes

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